Abstract

In order to synchronize timing for IEEE 802.16d orthogonal frequency division multiplexing (OFDM), this brief examines utility of multiplier less and DSP slice-based cross-correlation on Artix-7 FPGA. Given that these FPGAs have embedded DSP blocks, the obvious course of action shall be to apply conventional multiplier-based cross-correlation. This can, however, use a lot of DSP blocks, which might not be compatible with low-power devices. Therefore, in terms of power consumption and resource utilization, we compare four distinct quantization of multiplier less correlation to a DSP48E1 slice based device. Each system's OFDM temporal synchronization accuracy is assessed at various signal-to-noise ratios. The findings demonstrate that precise time synchronization may be achieved at high clock rates using even somewhat coarse multiplier less coefficient quantization. The end-to-end transceiver baseband proposed in this study is dynamically reconfigurable and can switch between three widely used OFDM standards: IEEE 802.11, IEEE 802.16, and IEEE 802.22. It may operate in a non-contiguous manner and switch quickly. The precision of an OFDM receiver's assessment of its carrier frequency offset (CFO) and symbol timing offset (STO) has a significant effect on its performance. This work presents a novel approach to OFDM synchronization that combines computational efficiency with resilient performance. The trade-off between the amount of computations to be done and the computation word length is investigated using FPGA prototype in terms of synchronization performance and power consumption. The proposed approach is demonstrated through simulation to offer precise STO and fractional CFO estimation across a variety of channels. Specifically, it can produce outstanding synchronization results when confronted with a CFO that beyond the capabilities of numerous advanced synchronization systems. When compared to current methods, the system implementation shows efficient resource usage and reduced power consumption; this is investigated as a fine-grained trade-off between performance and power consumption. The ultimate result is a reliable technique that can be utilized with less accurate analog front ends in low-power radios. The FFT and IFFT are explored using floating point operations to get accuracy symbols and their sizes and Compressive Sensing (CS) algorithm to reduce the data size with minimal hardware resources. The proposed OFDM wireless front end module has been validated for signals and images transmissions and results proved that 23% improvement in throughput, 12% reduction in power and 8% improvement in processing time.