Abstract

In this paper, efforts are devoted to designing hardware for important security algorithms that have a high level of security as a result of their internal architecture and are designed to be secure against current and future attacks. These algorithms, called MARS, Twofish and RC6, are one of the algorithms competing with the current standard (AES), and have been shortlisted among the top five. These algorithms are block ciphers with a block size of 128 bits, and the key length is variable. Both MARS and Twofish are based on the generalized Feistel structure, while RC6 is an improvement of RC5 that essentially uses data-dependent rotations. These algorithms are used in many applications due to their high security margin. The proposed hardware of the algorithms is designed using System Generator and Xilinx ISE 14.7, and implemented on a Xilinx Virtex-6 xc6vlx195t-3 FPGA board. The architecture of the proposed designs emphases on area utilization, thus following an iterative looping architecture that seeks to minimize resource and energy usage, making it suitable for applications that have limited resources. The implementation result was promising, as the maximum frequency, throughput, number of occupied slices, and power consumption were calculated, and compared to the current standard, AES, and its candidate Serpent algorithm.